1. Field of the Invention
The present invention relates to a method of evaluating a surface defect of a silicon wafer cut out from a silicon single-crystal ingot (which will be referred to as an ingot hereinafter). More particularly, the present invention relates to a silicon wafer surface defect evaluation method which facilitates manufacture of a defect-free region silicon wafer cut out from an ingot grown by a Czochralski method (which will be referred to as a CZ method hereinafter).
2. Description of the Related Art
With recent ultra-miniaturization of a semiconductor integrated circuit, as a factor which lowers a yield of a device, there is a crystal originated particle (which will be referred to as a COP hereinafter) which is a defect introduced in crystal growth, i.e., a defect formed in crystal growth of a silicon single-crystal ingot, a small defect of an oxygen precipitate which becomes a nucleus of an oxidation induced stacking fault (which will be referred to as an OISF hereinafter), or interstitial-type large dislocation (which will be referred to as L/D hereinafter).
The COP is a crystal originated pit which appears on a wafer surface when a mirror-polished silicon wafer is subjected to SC-1 cleaning using a mixed liquid of ammonia and hydrogen peroxide. When this wafer is measured by using a particle counter, this pit is detected as a particle (a light point defect, an LPD). The COP can be a factor which deteriorates electrical characteristics, e.g., time dependent dielectric breakdown (TDDB) characteristics of an oxide film, time zero dielectric breakdown (TZDB) characteristics and others. Further, when the COP exists on a wafer surface, steps may be generated in a device wiring process, resulting in disconnection. Furthermore, the COP can be a factor of leak or the like in an element isolation portion to lower a yield of a product.
In regard to the OISF, it is considered that a small oxygen precipitate formed in crystal growth is a nucleus, and the OISF is a stacking fault which is elicited in a thermal oxidation process or the like in manufacturing a semiconductor device. This OISF causes a defect, e.g., an increase in a leak current of a device. The L/D is also called a dislocation cluster or a dislocation pit since an etching pit having a direction is generated when a silicon wafer having this defect is dipped in a selective etchant mainly containing fluorinated acid. This L/D can be also a factor which deteriorates electrical characteristics, e.g., leak characteristics, isolation characteristics and others.
Based on the above-described facts, it is necessary to reduce the COP, the OISF and the L/D from a silicon wafer which is used to manufacture a semiconductor integrated circuit. Although various methods exist as methods of evaluating such crystal defects, there has been disclosed a crystal defect evaluation method of a silicon single-crystal using a copper decoration method which contaminates a sample surface with copper, diffuses copper into the sample by a heat treatment and then rapidly cools the sample to elicit defects on the crystal surface as a method of evaluating a small defect in particular (see, e.g., Patent Reference 1). In this method disclosed in Patent Reference 1, a region where an OISF or a nucleus which becomes an OISF exist is detected.
Further, there has been disclosed a wafer defect analysis method comprising a step of forming an insulating film having a predetermined thickness on a bare wafer to form an insulating film whose thickness has been changed with respect to a defective part of the wafer and a step of destroying a part of the insulating film whose thickness has been changed on the defective part by electrolysis and decorating copper on the defective part (see, e.g., Patent Reference 2). In the method disclosed in Patent Reference 2, a defect on a semiconductor wafer subjected to crystal growth can be directly analyzed with the naked eye.
Patent Reference 1: Japanese Patent Application laid-open No. 2001-81000 (claim 1)
Patent Reference 2: Japanese Patent No. 3241296 (claim 1, paragraph [0015])
However, the evaluation method using the copper decoration method disclosed in Patent Reference 1 or Patent Reference 2 can detect a COP whose size is less than a detection lower limit of a particle counter, but it is complicated since many steps are required for measurement, and hence there has been a problem that an evaluation throughput is poor and a cost is high.